The present invention generally relates to the field of semiconductors. More particularly, the present invention relates to the formation of a very thin epitaxial layer on a more heavily-doped substrate. The present invention especially applies to the manufacturing of MOS transistors. It more specifically aims at MOS transistors having very small dimensions in which the gate length is significantly lower than one micrometer, for example, from less than 0.1 xcexcm to approximately 0.5 xcexcm.
FIG. 1 very schematically shows a cross-sectional view of a conventional MOS transistor. This MOS transistor is formed in an active area of a single-crystal silicon substrate 1 delimited by a thick oxide region 2. This thick oxide region has been shown as corresponding to a region obtained by oxide growth according to a so-called LOCOS technique. It could correspond to any known type of active area definition, for example hollowing of the silicon surface and oxide filling. The MOS transistor includes a gate 4 provided with lateral spacers 5, currently made of silicon oxide or nitride. Gate 4 is separated from the silicon surface by a gate oxide layer 6. The drain and the source are shown as being LDD-type, that is, including more lightly-doped regions 10 and 11 extending to the gate limits and more heavily-doped regions 12 and 13 substantially extending to the spacer limits. Conventionally, regions 10 and 11 are formed by implantation, using gate 4 as a mask, and regions 12 and 13 are formed by implantation, using gate 4 widened by spacers 5 as a mask.
In the shown case of an N-channel MOS transistor, the substrate is of type P and regions 10 to 13 are of type N. The operating mode of such MOS transistors is well known. When a voltage is applied to gate 4, the apparent type of conductivity of the surface substrate is inverted under the gate region and an inversion or depletion layer forms, which constitutes a channel region between regions 10 and 11. This channel ensures a conduction between the source and the drain if a proper voltage is applied between source and drain.
As is known, this MOS transistor is subject to various parasitic effects and especially to the xe2x80x9cpunch-throughxe2x80x9d phenomenon. Punch-through especially occurs when the doping under the gate is such that, for a certain gate voltage, the inverted area under the gate extends deeply between heavily-doped source and drain regions 12 and 13. As a result of the punch-through effect, the MOS transistor does not turn back off. if the voltage remains applied between source and drain while the gate voltage is interrupted.
When the MOS transistor has minimum dimensions higher than one micrometer, the drain-substrate and source-substrate junctions are relatively deep and this punch-through phenomenon can be avoided by known means. Conversely, when the dimensions of the MOS transistor become significantly submicronic (that is, when the gate length becomes lower than one micrometer, for example, from on the order of less than 0.1 xcexcm to approximately 0.5 xcexcm), all the transistor dimensions are reduced accordingly and, especially, the junctions become very shallow. For example, junction depth x1 of regions 10 and 11 can be on the order of 50 nm (500 angstrxc3x6ms) and junction depth x2 of regions 12 and 13 can be on the order of 200 nm. In such conditions, the punch-through phenomenon is particularly acute.
One of the known means to avoid punch-through consists of making, in the channel area, a more lightly-doped upper area followed by a more heavily-doped region (refer to European patent application 0 530 046 of SGS-Thomson Microelectronics INC.). Then, when the gate is excited, the depletion area is limited to the thickness of the less doped region and there is no inversion of the more doped region.
This means that it is desired to obtain a vertical doping profile under the gate such as that represented by curve 20 of FIG. 2 with a first doping level c1 when the depth is lower than x0, depth x0 being lower than junction depth x1, and a second clearly higher level of doping c2 at least in a region determined beyond depth x0.
Further, obtaining of such a profile enables proper control of the threshold voltage and, if the lowest doping level is sufficiently low, to have high mobility in the channel.
However, if it is possible to obtain such a profile for devices of minimum dimensions on the order of one micrometer or even 0.5 xcexcm, this becomes impossible in practice with current techniques when the dimensions decrease. Indeed, to make a profile such as that illustrated in FIG. 2, a first more heavily-doped layer followed by a more lightly-doped layer, for example formed by epitaxy, have to be formed in the P substrate. However, during the subsequent anneals and especially during the drive-in anneals of the source and drain regions, there will be a drive-in of the P-type dopants under the gate and, instead of obtaining a very clear doping gradient such as that illustrated by curve 20, an attenuated gradient such as that designated by curve 21 is finally obtained.
Conventional means do not solve this problem when the desired value of x0 is, for example, on the order of 20 to 50 nm. Indeed, it is known to limit the outdiffusion of a buried layer under a relatively thick epitaxial layer by providing a large implantation of atoms such as nitrogen at a concentration of about 1018at./cm3 (U.S. Pat. No. 4,082,571) or in the range of 1018 to 1022at./cm3 (U.S. Pat. No. 4 956 693). For such nitrogen concentrations, a portion of the epitaxial layer is unavoidably impaired close to the interface with the underlying layer. Such methods have accordingly not been considered in case the thickness of the desired epitaxial layer is in the range of 20 to 50 nm.
Thus, an object of the present invention is to provide a method of obtaining of a doping profile with a very steep gradient, this doping profile remaining steep after thermal anneal operations.
Another object of the present invention is to apply this method to the manufacturing of a MOS transistor of very small dimension (less than 0.1 to 0.5 micrometer of gate length).
The present invention also aims at a MOS transistor obtained by the method of the present invention.
To achieve these and other objects, the present invention provides a method of manufacturing an area of the first type of conductivity with a steep doping gradient across the thickness, including the steps of providing a single-crystal semiconductor substrate, coating the substrate with a thin oxide layer implanting nitrogen in the upper surface of the substrate the nitrogen dose is approximately between 5.1013 and 5.1015at./cm2, annealing, and growing an epitaxial layer of lower doping level than the substrate, or an intrinsic layer.
According to an embodiment of the present invention, the method includes using a substrate of any type of conductivity and performing a nitrogen implantation and an implantation of atoms of the dopant of a first type of conductivity, before making an epitaxial layer of the first type of conductivity of low doping level, or an intrinsic layer.
According to an embodiment of the present invention, the nitrogen dose is comprised between 1 and 10.1014at./cm2, and preferably between 3 and 7.1014at./cm2.
According to an embodiment of the present invention, the nitrogen is implanted at an energy on the order of 10 keV.
According to an embodiment of the present invention, the epitaxial layer has a thickness on the order of 30 to 60 nm.
This method applies to the manufacturing of the area located under the gate of a MOS transistor from a substrate of the first type of conductivity.
Thus, the present invention also aims at an LDD-type MOS transistor including, under its gate area, a first lightly-doped region followed by a second region of the same type of conductivity of higher doping level with a significant doping gradient between the two regions, in which the interface area between the two regions contains nitrogen atoms.
According to an embodiment of the present invention, the first region extends down to a depth substantially equal to or lower than the depth of the LDD-type lightly-doped drain and source regions.